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1 single or multiple cell li-ion battery powered 4-channel and 6-channel led drivers isl97692, isl97693, isl97694a the isl97692, isl97693, isl97 694a are intersil?s highly integrated 4- and 6-channel led drivers for display backlighting. these parts maximize battery life by featuring only 1ma quiescent current, and by operating down to 2.4v input voltage, with no need for higher voltage supplies. the isl97692 has four channels and provides 8-bit pwm dimming with adjustable dimming frequency up to 30khz. the isl97693 has six channels with direct pwm dimming control. the isl97694a has 6 channels and provides 8-, 10-, or 12-bit pwm dimming with adjustable dimming frequency up to 30khz, 7.5khz, or 1.875khz, respectively, controlled with i 2 c or pwm input. the isl97692 and isl97694a feature phase shifting that may be enabled optionally, providing an optimized phase delay between channels. in the isl97692 and isl97694a, phase shifting can multiply the effect ive dimming frequency by four and six allowing above audio-ba nd pwm dimming with 10-bit dimming resolution. the isl97692, isl97693, isl97 694a employ adaptive boost architecture, which keeps the headroom voltage as low as possible to maximize battery life while allowing ultra low dimming duty cycle as low as 0.005% at 100hz dimming frequency in direct pwm mode. the isl97692, isl97693, isl97694a incorporate extensive protection functions including string open and short circuit detections, ovp, and otp. the isl97692, isl97693 are offered in the 16 ld 3x3mm tqfn package, and a 16 bump 1.7x1.7mm wlcsp for the isl97692. the isl97694a is offered in the 20 ld 3x4mm tqfn package. all parts operate in ambient temperature range of -40c to +85c. features ? 2.4v minimum input voltage, supports single cell applications ? 4 channels, up to 40ma each (isl97692) or 6 channels, up to 30ma each (isl97693, isl97694a) ? 90% efficient at 6p5s, 3.7v and 20ma (isl97693, isl97694a) ? low 0.8ma quiescent current ? pwm dimming control with internally generated clock - 8-bit resolution with adjustable dimming frequency up to 30khz (isl97692, isl97694a) - 12-bit resolution with adjust able dimming frequency up to 1.875khz (isl97694a) - optional automatic channel phase shift (isl97692, isl97694a) - linear dimming from 0.025%~100% up to 5khz or 0.4%~100% up to 30khz (isl97692, isl97694a) ? direct pwm dimming with 0.005% minimum duty cycle at 100hz ? 2.5% output current matching ? adjustable switching freque ncy from 400khz to 1.5mhz applications ? tablet, notebook pc and smart phone displays led backlighting related literature ? an1733 ?isl97694airt-evz evalua tion board user guide? ? an1734 ?isl97693airt-evz evalua tion board user guide? ? an1735 ?isl97692 evaluation board user guide? coming soon. figure 1. isl97694a typical application diagram figure 2. ultra low pwm dimming linearity fsw fpwm agnd ovp vin sda/pwmi iset comp scl d1 ch1 ch2 ch3 ch4 pgnd lx vin: 2.4v~5.5v vout: 24.5v, 6 x 20ma ch5 ch6 l1 10h 12k 15nf 10 1f 4.7f 4.7f 470k 23.7k 143k 291k 53k 100pf 2.2nf isl97694a 4.7f en 0.0001 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 input dimming duty cycle (%) iled (ma) f pwm : 200hz f pwm : 100hz may 1, 2014 fn7839.5 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2012, 2014. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl97692, isl97693, isl97694a 2 fn7839.5 may 1, 2014 submit document feedback table of contents typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pin configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 theory of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 pwm boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 dimming controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 direct pwm dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 phase shift control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 pwm dimming frequency adju stment (isl97692, isl97694a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 current matching and current accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 dynamic headroom control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 soft-start and power on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 power-off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 operation with input voltage greater than 5.5v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 smbus/i 2 c communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 write byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 read byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 slave device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 smbus/i 2 c register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 input capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 overvoltage protection (ovp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 boost output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 inductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 schottky diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 unused led channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 dimming mode setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 high current applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 pcb layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 pcb layout with tqfn and wlcsp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 general power pad design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 fault protection and monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 short circuit protection (scp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 open circuit protection (ocp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 overvoltage protection (ovp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 over-temperature protection (otp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
isl97692, isl97693, isl97694a 3 fn7839.5 may 1, 2014 submit document feedback typical application circuits figure 3. isl97692 typical application diagram - 4p7s figure 4. isl97693 typical application diagram - 6p7s fsw fpwm agnd ovp vin enps iset comp pwmi d1 ch1 ch2 ch3 ch4 pgnd lx v in : 2 .4v ~5.5v v out : 24 .5v , 4 x 20 ma l1 10h 12k 15nf 10 1f 4.7 f 4.7f 470 k 23 .7k 143 k 291 k 53k 100pf 2.2nf isl97692 4.7f en fsw agnd ovp vin pwmi iset comp d1 ch1 ch2 ch3 ch4 pgnd lx v in : 2.4v ~5.5v v out : 24.5v, 6 x 20ma ch5 ch6 l1 10h 12k 15nf 10 1f 4.7 f 4.7f 470 k 23 .7k 143 k 53k 100pf 2.2nf isl97693 4.7f en
isl97692, isl97693, isl97694a 4 fn7839.5 may 1, 2014 submit document feedback figure 5. isl97694a typical application diagram- 6p7s typical application circuits (continued) fsw fpwm agnd ovp vin sda/pwmi iset comp scl d1 ch1 ch2 ch3 ch4 pgnd lx v in : 2 .4v ~5.5v v out : 24.5v, 6 x 20ma ch5 ch6 l1 10h 12k 15nf 10 1f 4.7 f 4.7f 470k 23.7k 143 k 291 k 53k 100 pf 2.2nf isl97694a 4.7f en
isl97692, isl97693, isl97694a 5 fn7839.5 may 1, 2014 submit document feedback block diagrams figure 6. isl97692 block diagram ref gen vin gm amp comp + - ch1 ch4 pwm/ pfm logic fet drivers ovp reg osc & ramp comp imax ilimit highest vf string detect temp sensor enps iset + - o/p short ref_ ovp ref_ vsc internal bias + - open ckt, short ckt detection 1 dynamic headroom control ovp 4 fsw pwmi phase shift & pwm dimming controller 2 3 24v, 4x40ma lx v in : 2.4v to 5.5v fpwm optional fuse 8-bit digitizer direct pwm detect 10h en 8-bit dac isl97692 ch2 ch3 pgnd
isl97692, isl97693, isl97694a 6 fn7839.5 may 1, 2014 submit document feedback figure 7. isl97693 block diagram block diagrams (continued) ref gen vin gm amp comp + - ch1 ch4 pwm/ pfm logic fet drivers ovp reg osc & ramp comp imax ilimit highest vf string detect temp sensor iset + - o/p short ref_ ovp ref_ vsc internal bias + - open ckt, short ckt detection 1 dynamic headroom control ovp 6 fsw pwm dimming controller 2 3 24v, 6x30ma lx v in : 2.4v to 5.5v optional fuse 10h en 8-bit dac pgnd isl97693 ch2 ch3 4 5 ch6 ch5 pwmi
isl97692, isl97693, isl97694a 7 fn7839.5 may 1, 2014 submit document feedback figure 8. isl97694a block diagram block diagrams (continued) ref gen vin gm amp comp + - ch1 ch4 pwm/ pfm logic fet drivers ovp reg osc & ramp comp imax ilimit highest vf string detect temp sensor iset + - o/p short ref_ ovp ref_ vsc internal bias + - open ckt, short ckt detection 1 dynamic headroom control ovp 6 fsw scl phase shift & pwm dimming controller 2 3 24v, 6x30ma lx v in : 2.4v to 5.5v fpwm optional fuse i 2 c controller direct pwm detect 10h en 8-bit dac pgnd isl97694a ch2 ch3 4 5 ch6 ch5 sda/pwmi
isl97692, isl97693, isl97694a 8 fn7839.5 may 1, 2014 submit document feedback s pin configurations isl97692 (16 ld tqfn) top view isl97692 (1.7x1.7x0.53mm, 16 ball, 0.4mm pitch wlcsp) top view isl97693 (16 ld tqfn) top view isl97694a (20 ld tqfn) top view 1 2 3 4 12 11 10 9 5 6 7 8 16 15 14 13 agnd comp iset enps pwmi en vin fpwm ch4 ch3 ch2 ch1 ovp fsw pgnd lx thermal pad a c b 2 d 43 1 ch4 ch3 ch2 ch1 agnd comp enps iset pwmi en vin lx pgnd ovp fsw fpwm 1 2 3 4 12 11 10 9 5 6 7 8 16 15 14 13 ch5 ch6 agnd comp iset pwmi en vin ch4 ch3 ch2 ch1 ovp fsw pgnd lx thermal pad sda/pwmi iset pgnd nc en vin ch4 ch5 ch3 fpwm ovp agnd fsw ch2 ch6 comp scl lx 1 2 3 4 5 78910 15 14 13 12 11 20 19 18 17 6 nc 6 ch1 16 thermal pad
isl97692, isl97693, isl97694a 9 fn7839.5 may 1, 2014 submit document feedback pin descriptions pin name isl97692 isl97693 isl97694a description tqfn wlcsp agnd 1 c4 3 2 analog ground for precision circuits. ch5 - - 1 20 channel 5 current sink and channel monitoring. tie pin to gnd if channel unused. ch6 - - 2 1 channel 6 current sink and channel monitoring. tie pin to gnd if channel unused. comp 2 b4 4 3 external compensation. fit a series rc comprising 12k ? and 15nf from comp to gnd. iset 3 c3 5 4 channel current setting. the led ch annel current is adjusted from 2ma to 40ma (isl97692) or to 30ma with (isl97693, isl97694a) resistor r set from iset pin to gnd. enps 4 a4 - - enable phase shift pwm dimming control. high = enable. low = disable. pwmi 5 b3 6 - pwm input signal for isl97692/3 for brightness control. scl (isl97694a) --- 5i 2 c serial clock input. mode selection to pwmi input when tied to gnd for isl97694a. sda/pwmi (isl97694a) --- 7i 2 c serial data input and output. pwmi input when scl tied to gnd for isl97694a. en 6 a2 7 8 enable input. high = normal operation. low = shutdown. vin 7 b2 8 9 input supply voltage. fpwm 8 a3 - 10 tie fpwm to vin to select direct pwm mode. in direct pwm mode, the channel outputs follow the pwmi pin?s frequency and pulse width. connect resistor r fpwm from fpwm to gnd to select pwm dimming frequency adjustment. in this mode, the channel outputs follow the pwmi pin?s pwm duty, and the led pwm dimming frequenc y is set by the value of resistor r fpwm . lx 9a19 11input to boost switch. pgnd 10 b1 10 12 power ground (lx, c in , and c out power return). fsw 11 c2 11 14 switching frequency adjustment. the boost switching frequency is adjusted from 400khz to 1.5mhz with resistor r fsw from fsw pin to gnd. ovp 12 c1 12 15 overvoltage protection input. ch1 13 d1 13 16 channel 1 current sink and channel monitoring. tie pin to gnd if channel unused. ch2 14 d2 14 17 channel 2 current sink and channel monitoring. tie pin to gnd if channel unused. ch3 15 d3 15 18 channel 3 current sink and channel monitoring. tie pin to gnd if channel unused. ch4 16 d4 16 19 channel 4 current sink and channel monitoring. tie pin to gnd if channel unused. nc - - - 6, 13 not connected internally. pad - connect to pgnd and refer to the figure 32 in the general power pad design considerations.
isl97692, isl97693, isl97694a 10 fn7839.5 may 1, 2014 submit document feedback ordering information part number (notes 1, 4) part marking temp range (c) package (pb-free) pkg. dwg. # isl97692irtz (note 2) 7692 -40 to +85 16 ld 3x3x0.75mm tqfn l16.3x3d ISL97692IIZ-T (note 3) 7692 -40 to +85 16 bump 1.7x1.7mm, 0.4mm pitch wlcsp w4x4.16b isl97693irtz (note 2) 7693 -40 to +85 16 ld 3x3x0.75mm tqfn l16.3x3d isl97694airtz (note 2) 694a -40 to +85 20 ld 3x4x0.8mm tqfn l20.3x4a isl97692irtz-evalz evaluation board for tqfn isl97692iiz-evz evaluation board for wlcsp isl97693irtz-evalz evaluation board for tqfn isl97694airt-evz evaluation board for tqfn notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. these intersil pb-free wlcsp and bga packaged products employ special pb-free material sets; molding compounds/die attach mat erials and snagcu - e1 solder ball terminals, which are rohs compliant an d compatible with both snpb and pb-free soldering operations. int ersil pb-free wlcsp and bga packaged products are msl classified at pb-free pe ak reflow temperatures that meet or exceed the pb-free requirem ents of ipc/ jedec j std-020. 4. for moisture sensitivity level (msl), please see device information page for isl97692 , isl97693, isl97694a . for more information on msl please see tech brief tb363 .
isl97692, isl97693, isl97694a 11 fn7839.5 may 1, 2014 submit document feedback absolute maximum ratings (note 5) thermal information vin, iset, comp, ovp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v pwmi, fpwm, fsw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v en, enps, scl, sda/pwmi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v ch1 to ch6, lx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 28v pgnd, agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v maximum average current into lx pin for tqfn . . . . . . . . . . . . . . . . . .2.6a maximum average current into lx pin for csp . . . . . . . . . . . . . . . . . . . . 1a esd ratings human body model (tested per jesd22-a114f) (isl97692, isl97693) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kv human body model (tested per jesd22-a114f) (isl97694a) . . .2.5kv machine model (tested per jesd22-a115c) . . . . . . . . . . . . . . . . . . 200v charged device model (jesd22-c101e) . . . . . . . . . . . . . . . . . . . . . . . 2kv latch up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . 100ma recommended operating conditions input voltage (v in ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4v to 5.5v output voltage (v out ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .up to 26v ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c thermal resistance (typical) ? ja (c/w) ? jc (c/w) 16 ld tqfn (notes 6, 7) . . . . . . . . . . . . . . . 51 4.6 20 ld tqfn (notes 6, 7) . . . . . . . . . . . . . . . 45 3.0 16 bump wlcsp (note 6) . . . . . . . . . . . . . . 82 n/a thermal characterization (typical) (note 8) psi jt (c/w) 16 ld tqfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.11 20 ld tqfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1 thermal characterization (typical) psi jb (c/w) 16 bump wlcsp (note 9) . . . . . . . . . . . . . . . . . . . . . . . . 22 maximum continuous junction temperature . . . . . . . . . . . . . . . . .+125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. voltage ratings are all with respect to the agnd pin. 6. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 7. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 8. psi jt is the psi junction-to-top thermal characterization parameter. if the package top temperature can be measured with this rating then the die junction temperature can be estimated more accurately than the ? jc and ? jc thermal resistance ratings. 9. psi jb is the psi junction-to-board thermal characterization parameter. electrical specifications v in = en = 3.3v, t a = +25c unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c. parameter description condition min (note 10) typ max (note 10) unit general v in backlight supply voltage, (notes 11, 12) t a = +25c 2.4 5.5 v i vin_standby standby current en = low, ldo disabled 1 a i vin v in active current, i led = 40ma (isl97692) 30ma (isl97693/(isl97694a) all channels 100% duty 2.5 ma all channels 0% duty 0.8 ma v out output voltage v in ? 2.7v, i led = 40ma (isl97692) 30ma (isl97693/4a) 26 v v uvlo undervoltage lockout threshold 2 2.15 2.35 v v uvlo_hys undervoltage lockout hysteresis 150 mv enlow en input low voltage 0.5 v enhi en input high voltage 1.5 v boost switching regulator ss soft-start 100% led duty cycle 7 ms swilimit boost fet current limit for qfn 2.7v< v in < 5.5v, f sw = 600khz, l = 10h, t a +55c 2.45 2.8 3.2 a boost fet current limit for csp 1.2a 1.6a a r ds(on) internal boost switch on-resistance t a = +25c 212 m ?
isl97692, isl97693, isl97694a 12 fn7839.5 may 1, 2014 submit document feedback eff_peak peak efficiency v in = 5.5v, v out = 21v, t a = +25c, r fsw = 144k ?? i ch1-ch6 = 20ma, l = 10h with dcr ?? 150m 90 % v in = 2.7v, v out = 21v, t a = +25c, r fsw = 144k ?? i ch1-ch6 = 20ma, l = 10h with dcr ?? 150m 76 % d max boost maximum duty cycle f sw = 400khz 93.5 % f sw = 1.5mhz 93 % d min boost minimum duty cycle f sw = 400khz 11 % f sw = 1.5mhz 15 % f sw boost switching frequency r fsw = 216k 360 400 440 khz r fsw = 72.1k 1.2 mhz r fsw = 57.7k 1.35 1.5 1.65 mhz ilx_leakage lx leakage current lx = 26v 10 a reference i match channel-to-channel dc current matching i led = 20ma -2.5 +2.5 % i acc current accuracy i led = 20ma -3 +3 % fault detection v sc channel short circuit threshold 6.75 8 9.25 v v temp over-temperature threshold 150 c v ovplo overvoltage limit on ovp pin 1.180 1.22 1.245 v ovp fault ovp short detection fault level 75 mv current sources v headroom dominant channel current source headroom at ch pin i led = 20ma t a = +25c 300 mv i led(max) maximum led current per channel 2.7v < v in < 5.5v, v out = 21v (isl97692 qfn) 40 ma 2.7v < v in < 5.5v, v out = 21v (isl97692 wlcsp, isl97693, and isl97694a) 30 ma pwm generator v il guaranteed range for pwm input low voltage 0.5 v v ih guaranteed range for pwm input high voltage 1.5 v f pwmi pwmi input and output frequency range 8-bit dimming resolution 100 30,000 hz 10-bit dimming resolution 100 7.5 khz 12-bit dimming resolution 100 1.87 khz dpwm acc direct pwm dimming output resolution (isl97692, isl97693 and isl97694a) 80 ns t dpwm_on_min direct pwm dimming minimum on-time (isl97692, isl97693 and isl97694a) 350 ns pwm acc pwm dimming with adjustable dimming frequency output resolution (isl97692, isl97694a) 8 bit isl97694a, en10bit = 1 10 bit isl97694a, en12bit = 1 12 bit f pwm generated pwm dimming frequency range (isl97692, isl97694a) 100 30,000 hz electrical specifications v in = en = 3.3v, t a = +25c unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter description condition min (note 10) typ max (note 10) unit
isl97692, isl97693, isl97694a 13 fn7839.5 may 1, 2014 submit document feedback smbus/i 2 c interface (isl97694a only) vil guaranteed range for data, clock input low voltage 0.5 v vih guaranteed range for data, clock input high voltage 1.5 vdd v vol smbus/i 2 c output data line logic low voltage i pullup = 4ma 0.17 v i leak input leakage on sda/scl measured at 4.8v -10 10 a smbus/i 2 c timing specifications (isl97694a only) ten-smbus/i 2 c minimum time between vin>uvlo and smbus/i 2 c enabled 2 ms f scl scl clock frequency 400 khz t buf bus free time between stop and start condition 1.3 s t hd:sta hold time after (repeated) start condition aft er this period, the first clock is generated 0.6 s t su:sta repeated start condition setup time 0.6 s t su:sto stop condition setup time 0.6 s t hd:dat data hold time 300 ns t su:dat data setup time 100 ns t high low period of scl clock 1.3 s t low high period of scl clock 0.6 s t f clock/data fall time 300 ns t r clock/data rise time 300 ns notes: 10. parameters with min and/or max limits are 100% tested at +25c , unless otherwise specified. te mperature limits established b y characterization and are not production tested. 11. at maximum v in of 5.5v, minimum v out is 6v. minimum v out can be lower at lower v in . 12. limits established by characterization and are not production tested. electrical specifications v in = en = 3.3v, t a = +25c unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter description condition min (note 10) typ max (note 10) unit
isl97692, isl97693, isl97694a 14 fn7839.5 may 1, 2014 submit document feedback typical performance curves figure 9. efficiency vs v in (i ch : 20ma, f dim : 200hz, for leds: 6p5s, 6p6s, 6p7s) figure 10. efficiency vs pwm dimming (v in : 3.7v, i ch : 20ma, f dim : 200hz, for leds: 6p5s, 6p6s, 6p7s) figure 11. pwm dimming linearity (v in : 3.7v, v out : 21v for 6p7s, f dim : 200hz) figure 12. channel matching accuracy (v in : 3.7v, v out : 21v for 6p7s, i ch : 20ma) figure 13. start-up (100% direct pwm dimming, v in : 3.7v, i ch : 20ma, leds: 6p7s, f dim : 200hz) figure 14. start-up (100% decoded pwm dimming, v in : 3.7v, i ch : 20ma, leds: 6p7s, f dim : 200hz) 76 78 80 82 84 86 88 90 92 2.7 3.2 3.7 4.2 4.7 5.2 input voltage (v) efficiency (%) 6p7s leds 6p6s leds 6p5s leds pwm dimming (%) efficiency (%) 50 55 60 65 70 75 80 85 90 95 0 20 40 60 80 100 6p7s leds 6p5s leds 6p6s leds 0 5 10 15 20 0 20406080100 input dimming duty cycle (%) led current (ma) -2.5 -1.5 -0.5 0.5 1.5 2.5 01234567 channel number matching accuracy (%) ic#1 ic#2 ic#3 i l v out v lx v ch i l v out v lx v ch
isl97692, isl97693, isl97694a 15 fn7839.5 may 1, 2014 submit document feedback figure 15. start-up (50% direct pwm dimming, v in : 3.7v, i ch : 20ma, leds: 6p7s, f dim : 200hz) figure 16. start-up (50% decoded pwm dimming, v in : 3.7v, i ch : 20ma, leds: 6p7s, f dim : 200hz) figure 17. minimum dimming duty cycle (0.003% direct pwm dimming mode, f dim :100hz) figure 18. i 2 c control timing and channel current (100% dimming, isl97694a) figure 19. decoded pwm dimming with phase shift (v in : 3.7v, i ch : 20ma, dim: 17%, f dim : 250hz, leds: 6p6s) figure 20. direct pwm dimming without phase shift (v in : 3.7v, i ch : 20ma, dim: 17%, f dim : 250hz, leds: 6p6s) typical performance curves (continued) i l v out v lx v ch i l v out v lx v ch i ch pwm input s:start p:stop scl sda i_ch slave address:01011010 r/w a brightness(100%): 11111111 command code (8bit) a a v_lx i_l v_ch1 v_ch2 i l v ch1 v lx v ch2 v lx i l v ch2 v ch1
isl97692, isl97693, isl97694a 16 fn7839.5 may 1, 2014 submit document feedback theory of operation pwm boost converter the current mode pwm boost converter produces the minimal voltage needed to enable the led stack with the highest forward voltage drop to run at the programmed current. the isl97692, isl97693, isl97694a employs current mode control boost architecture that has a fast curr ent sense loop and a slow voltage feedback loop. this architecture achieves the fast transient response, which is essential for portable product backlight applications where the backlight must not flicker when the power source is changed from a drained battery to an ac/dc adapter. the number of leds that can be driven by isl97692, isl97693, isl97694a depends on the type of led chosen in the application. the maximum output is 26v at 40ma from 2.7v input. enable take the en input high to enable the isl97692, isl97693, isl97694a for normal operatio n and low to enter low-power shutdown, which immediately turns off led channels and the boost regulator. dimming controls the isl97692, isl97693, isl97694a allows the led current to be programmed in the range 2ma to 40ma (isl97692) or 2ma to 30ma (isl97693, isl97694a) by r set per equation 1: where: - 1066 is a constant determined by design -r set is the resistor from iset pin to gnd ( ? -i ledmax is the peak current set by resistor r set (a) for example, if the required led current (i ledmax ) is 40ma, then the r set value needed is: choose the nearest standard resistor: 26.65k ??? 0.1% direct pwm dimming the isl97693 always operates in direct pwm dimming mode. the isl97692 and isl97694a can be selected to operate in direct pwm dimming mode by co nnecting the fpwm pin to vin and the scl pin of isl97694a must be tied to gnd. with direct pwm, the channel outputs follow the input pwm signal frequency and pulse width, as provided to the pwmi pin. when pwmi is high, all channels sink the current set by the r set resistor. when pwmi is low, all channels are high-z. the maximum allowed input pwm frequency at pwmi is 30khz. the minimum duty is calculated by equation 3 according to the input pwm frequency, and is set by the minimum channel on-time of 350ns. for example, for a 200hz input pwm frequency, the minimum duty cycle is: the resolution is calculated by equation 5 according to the input pwm frequency, and the fixed 80 ns resolution of isl97692, isl97693, isl97694a. thus the effective resolution at 200hz is 15.9 bits: phase shift control the isl97692, isl97694a are capa ble of delaying the phase of each current source. conventional led drivers exhibit the worst load transients to the boost circ uit by turning on all channels simultaneously, as shown in figures 21 and 23. in contrast, the isl97692, isl97694a phase shift each channel by turning them on once during each pwm di mming period, as shown in figures 22 and 24. at each dimming duty cycle (except at 100%) the sum of the phase shifted to tal current will be less than a conventional led drivers? total current. for the isl97692, isl97694a, the channels are separated by 360/n, where n is number of channels enabled. for example, if three channels are enabled, they will be separated by 120. if the channels are combined for higher current application, the phase shift function must be di sabled by connecting the enps pin to ground. i ledmax 1066 r set --------------- = (eq. 1) r set 1066 0.04 ? 26.65k ? == (eq. 2) (eq. 3) min duty cycle 350ns input pwm frequency ? = (eq. 4) min duty cycle 350ns 200hz ? 0.007% == (eq. 5) pwm resolution 1 80ns input pwm frequency ? ------------------------------------------------------------------------------- = (eq. 6) pwm resolution 1 80ns 200hz ? -------------------------------------- 62500 15.9bits = = = figure 21. conventional 4-ch led driver with 10% pwm dimming channel current (upper) and total current (lower) iled1-20ma iled_total_80ma time (ms) iled2-20ma iled3-20ma iled4-20ma 51015
isl97692, isl97693, isl97694a 17 fn7839.5 may 1, 2014 submit document feedback pwm dimming frequency adjustment (isl97692, isl97694a) the isl97692 and isl97694a can use an internal oscillator to generate the pwm dimming frequenc y. in this mode, the duty of the signal at pwmi pin is measured with 8-, 10- or 12-bit resolution, and applied to the internally generated pwm dimming frequency. the dimming frequency is set by an external resistor r fpwm at the fpwm pin for isl97692 and isl97694a, per equation 7: where: - r0 is determined by design - r0 = 58.1 x 10 6 for 8-bit - r0 = 14.5 x 10 6 for 10-bit - r0 = 36.2 x 10 5 for 12-bit -f pwm is the required pwm dimming frequency (hz) -r fpwm is the resistor from fpwm pin to gnd ( ?? for example, to set the pwm dimming frequency to 480hz at 8-bit resolution: the maximum allowed input and output pwm dimming frequency varies according to the pwm resolution, per table 1. this is configurable for the isl97694a by the en12bit and en10bit bits in register 0x01. figure 22. isl97692 phase shift 4-channels led driver with 10% pwm dimming channel current (upper) and total current (lower) iled1-20ma iled_total_20ma time (ms) iled2-20ma iled3-20ma iled4-20ma 5 10 figure 23. conventional led driver pwm dimming channel and total current at 50% duty cycle iled4-20ma iled_total_80ma time (ms) iled3-20ma iled2-20ma iled1-20ma 5 10 figure 24. isl97692 phase shif t led driver pwm dimming channel at 50% duty cycle iled4-20ma iled_total_40ma time (ms) iled3-20ma iled2-20ma iled1-20ma 5 10 table 1. max pwm dimming frequency set by r fpwm part max frequency (khz) pwm resolution (bit mode) isl97692 30 8 isl97694a 30 8 7.5 10 1.875 12 figure 25. isl97692 4 -channels phase shift timing illustration iled1 iled2 iled3 iled4 iled1 t on pwmi 60% 40% 60% 40% t pwmin t fpwm (t pwmout ) t off r fpwm r0 f pwm ----------------- = (eq. 7) r fpwm 58.1 6 ? 10 480 ----------------------- - 121k ? = = (eq. 8)
isl97692, isl97693, isl97694a 18 fn7839.5 may 1, 2014 submit document feedback current matching and current accuracy each channel of the led current is regulated by a current sink circuit. the led peak current is set by the external r set resistor according to equation 1. the current sink mosfets in each led driver channel output are designed to run at ~300mv to optimize power loss versus accuracy requir ements. the sources of errors of the channel-to-channel curren t matching come from internal amplifier offsets, internal layout and reference accuracy. these parameters are optimized for cu rrent matching and absolute current accuracy. absolute accura cy is also determined by the external resistor r set , and so a 0.1% tolerance resistor is recommended. dynamic headroom control the isl97692, isl97693, isl97 694a features a proprietary dynamic headroom control circ uit that detects the highest forward voltage string or effectiv ely the lowest voltage on any of the channel pins. when this lowest channel voltage is lower than the short circuit threshold, v sc , such voltage will be used as the feedback signal for the boost regulator. the boost makes the output to the correct level, such that the lowest channel pin is at the target headroom voltage. si nce all led stacks are connected to the same output voltage, the other channel pins will have a higher voltage, but the regulated current source circuit on each channel will ensure that each ch annel has the same current. the output voltage will regulate cycle-by-cycle and it is always referenced to the highest forward voltage string in the architecture. soft-start and power on once the isl97692, isl97693, isl97694a are powered up and the en pin is taken high, the boost regulator will begin to switch and the current in the inductor will ramp-up. the current in the boost power switch is monitored and the switching is terminated in any cycle where the current exceeds the current limit. the isl97692, isl97693, isl97694a includes a soft-start feature where this current limit starts at a low value (350ma). this is stepped up to the final 2.8a current limit in seven further steps of 350ma. these steps will happen over typically 7ms, and will be extended at low led pwm frequenc ies if the led duty cycle is low. this allows the output capacitor to be charged to the required value at a low current limit and prevents high input current for systems that have only a low to medium output current requirement. note that there will be also an initial in-rush current to c out when v in is applied. this is determined by the ramp rate of v in and the values of c out and l power-off sequence operation with input voltage greater than 5.5v the isl97692, isl97693, isl97694a boost regulator can operate from an input voltage higher than 5.5v, and up to 23v, as long as an additional supply vo ltage between 2.4v and 5.5v is available for the vin pin. please refer to figure 26 for a typical application schematic adopting this solution. v in vo en pwmi ichn soft-start (7ms) feedback regulation established uvlo (rising) v in vo en pwmi ichn v uvlo - 150mv boost converter turned off t off after reaching {v uvlo - 150mv} depends on application
isl97692, isl97693, isl97694a 19 fn7839.5 may 1, 2014 submit document feedback smbus/i 2 c communications the isl97694a is controlled by smbus/i 2 c for pwm dimming, and powers up in the shutdown state. the isl97694a is enabled when both the en pin is high and the bl_ctl bit in register 0x01 is programmed to 1. write byte the write byte protocol is only three bytes long. the first byte starts with the slave address followed by the ?command code,? which translates to the ?register index? being written. the third byte contains the data byte that must be written into the register selected by the ?command code?. a shaded label is used on cycles during which the slaved backlight controll er ?owns? or ?drives? the data line. all other cycles are driven by the ?host master.? read byte as shown in figure 30, the four byte long read byte protocol starts out with the slave address followed by the ?command code?, which translates to the ?register index.? subsequently, the bus direction turns around with the rebroadcast of the slave address with bit 0 indicating a read (?r?) cycle. the fourth byte contains the data being returned by the backlight co ntroller. that byte value in the data byte reflects the value of the register being queried at the ?command code? index. note the bus directions, which are highlighted by the shaded label that is used on cycles during which the slaved backlight controller ?owns? or ?drives? the data line. all other cycles are driven by the ?host master.? slave device address the slave address contains 7 msb plus one lsb as r/w bit, but these 8 bits are usually called slave address bytes. as shown in figure 27, the high nibble of the slave address byte is 0x5 or b?0101? to denote the ?backlight controller class?. bit 0 is always the r/w bit, as specified by the smbus/i 2 c protocol. if the device is in the write mode where bit 0 is 0, the slave address byte is 0x5a or b?01011010?. if the device is in the read mode where bit 0 is 1, the slave address byte is 0x5b or b?01011011?. fsw fpwm agnd ovp vin sda/pwmi iset comp scl d1 ch1 ch2 ch3 ch4 pgnd lx v bat t : 2.4v~21.8v v out : 24 .5v , 6 x 20 ma ch5 ch6 l1 10 h 12k 15 nf 4.7f 4.7f 470 k 23 .7k 143k 291k 53 k 100 pf 2.2nf isl97694a 4.7f en 2.4v~5.5 v figure 26. led driver operation with input voltage up to 26v figure 27. slave address byte definition msb device identifier device address r e a d / w r i t e b i t r/w 0101101
isl97692, isl97693, isl97694a 20 fn7839.5 may 1, 2014 submit document feedback smbus/i 2 c register definitions the backlight controller register s are byte wide and accessible via the smbus/i 2 c read/write byte protocols. their bit assignments are provided in figures 29 and 30 with reserved bits containing a default value of ?0?. when the isl97694a is configured to 10-bit or 12-bit operation, write the pwm brightness control re gister lsb (address 0x02) first. the subsequent write of pwm br ightness control register msb (address 0x00) updates the contents of both registers to the pwm engine. figure 28. smbus/i 2 c interface for isl97694a v ih v il v ih v il t r t low t hd:sta t hd:dat t f t high t su:dat s s p p t su:sto smbdat smbclk notes: smbus/i 2 c description s = start condition p = stop condition a = acknowledge a = not acknowledge r/w = read enable at high; write enable at low t buf t su:sta figure 29. write byte protocol for isl97694a master to slave slave to master 171181811 s slave address w a command code a data byte a p figure 30. read byte protocol for isl97694a master to slave slave to master 1711811811811 s slave address w a command code a s slave address r a data byte ap
isl97692, isl97693, isl97694a 21 fn7839.5 may 1, 2014 submit document feedback component selection the design of the boost converte r is simplified by an internal compensation scheme allowing ea sy design without complicated calculations. please select your component values using the following recommendations. input capacitor it is recommended that a 4.7f to 10f x5r/x7r or equivalent ceramic input capacitor is used. overvoltage protection (ovp) the integrated ovp circuit monitors the boost output voltage, v out , and keeps the voltage at a safe le vel. the ovp threshold is set as equation 9: where: - 1.22v is the intended bandgap voltage by design -v ovp is the maximum boost output voltage, v out (v) - r1 is the resistor from ovp pin to the boost output ( ?? - r2 is the resistor from ovp pin to gnd ( ??? the total r1 plus r2 series resistance should be high to minimize power loss through the resistor network. for example, choosing r1 = 470k ? and r2 = 23.7k ? per the typical application circuits on page 3 and block diagrams on page 5. set v ovp (typ) to 25.41v (equation 10). the ovp threshold, r1, and r2 tolerances should also be taken into account (equations 11 and 12). calculating v ovp using the ovp threshold range (1.18v to 1.24v) and 0.1% resistor tolerances gives an actual v ovp range of 24.53v to 25.88v for the 25.4v previous example (equations 13 and 14). it is recommended that parallel capacitors are placed across the ovp resistors such that r1/r2 = c2/c1. using a c1 value of at least 30pf is recommended. these capacitors reduce the ac impedance of the ovp node, which reduces noise susceptibility when using high value resistors. boost output voltage range the working range of the boost output voltage, v out is from 40% to 100% of the maximum output voltage, v ovp , set by resistors r1 and r2, as described in the previous section. the target applications should be considered carefully to ensure that v ovp is not set unnecessarily high. for example, using r = 470k ? and r2 = 23.7k ? per the ?typical application circuits? on page 3 sets v ovp to between 24.53v to 25.88v when tolerances are considered. table 2. i 2 c register all locations for isl97694a address register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default value smbus/i 2 c protocol 0x00 pwm brightness control register msb brt11 brt10 brt9 brt8 brt7 brt6 br t5 brt4 0xff read and write 0x01 device control register - - - - en12bit en10bit ps_en bl_ctl 0x00 read and write 0x02 pwm brightness control register lsb brt3 brt2 brt1 brt0 - - - - 0xf0 read and write table 3. i 2 c register functions for isl97694a address register data bit descriptions 0x00 pwm brightness control register msb brt[11..4] = dpwm duty cycle brightness control in 8 bit pwm data mode, pwm data is brt[11..4] in 10 bit pwm data mode, pwm data is brt[11..2] in 12 bit pwm data mode, pwm data is brt[11..0] 0x01 device control register ps_en = phase shift on/off (1: phase shift enabled, 0: phase shift disabled) bl_ctl = backlight on/off (1: driver enable d if en pin is high, 0 = driver shutdown) {en12bit, en10bit} = {0,0} to select 8 bit pwm data mode {en12bit, en10bit} = {0,1} to select 10 bit pwm data mode {en12bit, en10bit} = {1,0} to select 12 bit pwm data mode 0x02 pwm brightness control register lsb brt[3.0] = dpwm duty cycle brightness control (10 and 12 bit pwm data modes only). note: this data is saved, but the pwm engine is only updated with brt[11..0] or brt[11..2] when the pwm brightness control register msb 0x00 is written v ovp min ?? 1.22v r1 r2 + r2 ---------------------- ? = (eq. 9) v ovp typ ?? 1.22v 470 23.7 + 23.7 --------------------------- - ? 25.41v == (eq. 10) v ovp min ?? 1.18v r1min r2max + r2max --------------------------------------------- - ? = (eq. 11) v ovp max ?? 1.24v r1max r2min + r2min --------------------------------------------- - ? = (eq. 12) v ovp min ?? 1.18v 470 0.999 ? ?? 23.7 1.001 ? ?? + 23.7 1.001 ? ?? ------------------------------------------------------------------------------- - ? 24.53v == (eq. 13) v ovp max ?? 1.24v 470 1.001 ? ?? 23.7 0.999 ? ?? + 23.7 0.999 ? ?? ------------------------------------------------------------------------------- - ? 25.88v == (eq. 14)
isl97692, isl97693, isl97694a 22 fn7839.5 may 1, 2014 submit document feedback the minimum voltage, v ovp (min) = 24.53v, sets the maximum number of leds per channel be cause this is the worst case minimum voltage that the boost converter is guaranteed to supply. the maximum voltage, v ovp (max) = 25.88v, sets the minimum number of leds per channel because it sets the lowest voltage that the boost converter is guaranteed to reach: 40% x 25.88v = 10.35v. using leds with a v f tolerance of 3v to 4v, this v ovp example is suitable for strings of 4 to 6 leds. if fewer than 4 leds per channel are specified, v ovp must be reduced. switching frequency the boost switching frequency is adjusted by resistor r fsw (equation 15): where: -8.65x10 10 is determined by design -f sw is the desirable boost switching frequency (hz) -r fsw is resistor from fsw pin to gnd ( ?? inductor choose the inductance according to table 4: the inductor saturation current ra ting should be as provided by equation 16: where: -i l is the minimum inductor sa turation current rating (a) -v out is the maximum output voltage set by ovp (v) -i led is the sum of the channel currents (a) -v in is the minimum input voltage (v) if the calculation produces a curr ent rating higher than the 3.08a maximum boost switch current limit, then a 3a inductor current rating is adequate. for example, for a system using 4 led channels with 30ma per channel and a maximum output volt age (ovp) of 24.53v with an input supply of 2.7v minimum as shown by equation 17: output capacitor it is recommended that a two of 4.7f x5r/x7r or equivalent ceramic output capacitor is used. schottky diode the schottky diode should be rated for at least the same forward current as the inductor, and for a reverse voltage equal to at least the maximum output voltage, ovp. compensation the isl97692, isl97693, isl97694a are boost regulator uses a current mode control architecture with a standardized external compensation network connected to the comp pin. the component values shown in the ?typical application circuits? on page 3, are ideal for most typical applications. the network comprises a series rc of 12k and 15nf from comp to gnd. applications unused led channels connect unused led channels to gnd. dimming mode setting high current applications each channel of the isl97692 supports 40ma continuous sink current. each channel of the isl97693, isl97694a supports 30ma continuous sink current. for applic ations that need higher current, multiple channels can be ganged together (tables 6 and 7). table 4. inductor selection boost frequency inductance (h) 400khz to 700khz 10 to 15 700khz to 1mhz 6.8 to 10 1mhz to 1.5mhz 4.7 to 8.2 1.5mhz 3.3 to 4.7 f sw 8.65 10 ? 10 ?? r fsw ------------------------------- - = (eq. 15) i l 1.35 v out i led ? ? v in ---------------------------------------------------- - = (eq. 16) i l 1.35 24.53 4 0.03 ? ?? ? ? 2.7 ---------------------------------------------------------------- - 1.47a == (eq. 17) table 5. dimming mode setting of isl97694a dimming mode scl sda /pwmi fpwm direct pwm gnd pwm v in phase shift pwm gnd pwm connect a resistor fpwm pin to gnd i 2 c control scl sda connect a resistor fpwm pin to gnd table 6. ganged isl97692 channels for higher current total channels channel current channel connections 4 40ma per channel ch1, ch2, ch3, ch4 2 80ma per channel {ch1 & ch2}, {ch3 & ch4} 1 160ma {ch1 & ch2 & ch3 & ch4} table 7. ganged isl97693, isl97694a channels for higher current total channels channel current channel connections 6 30ma per channel ch1, ch2, ch3, ch4, ch5, ch6 3 60ma per channel {ch1, ch2}, {ch3, ch4}, {ch5, ch6} 2 90ma per channel {ch1, ch2, ch3}, {ch4, ch5, ch6} 1 180ma {ch1, ch2, ch3, ch4, ch5, ch6}
isl97692, isl97693, isl97694a 23 fn7839.5 may 1, 2014 submit document feedback figure 31 shows ch1 and ch2 ganged for a high current application. pcb layout considerations pcb layout with tqfn and wlcsp package figures 33 and 34 shows the example of the pcb layout of isl97694a and isl97692 wlcsp. this type of layout is particularly important for this type of product, resulting in high-current flow in the main loop?s traces. careful attention should be focused in the following layout details: 1. the typical application diagram (figures 3, 4 and 5 on pages 3, and 4) the separation of pgnd and agnd is essential, keeping the agnd referenced only local to the chip. this minimizes switching nois e injection to the feedback sensing and analog areas, as well as eliminating dc errors form high-current flow in resistive pc board traces. 2. boost input capacitors, output capacitors, inductor and schottky diode should be placed together in a nice tight layout. keeping the grounds of the input, and output connected with low impedance and wide metal is very important to keep these nodes closely coupled. 3. if possible, try to maintain central ground node on the board and use the input capacitors to avoid excessive input ripple for high output current supplies. the filtering capacitors should be placed close by the vin pin. 4. careful consideration should be taken with any traces carrying high di/dt pulsating signals. trac es carrying high di/dt pulsating signals should be kept as short and as tight as possible. the current loop generates a magnetic field which can couple to another conductor inducing unwanted voltage. components should be placed such that current flows through them in a straight line as much as possible. this will help reduce size of loops and reduce the emi from the pcb. 5. if trace lengths are long, the re sistance of the trace increases and can cause some reduction in ic efficiency, and can also cause system instability. traces carrying power should be made wide and short. 6. in discontinuous conduction mode , the direction of the current is interrupted every few cycles. this may result in large di/dt (transient load current). when in jected in the ground plane the current may cause voltage drops, which can interfere with sensitive circuitry. the analog gr ound and power ground of the ic should be connected very close to the ic to mitigate this issue 7. for optimum load regulation and true v out sensing, the ovp resistors should be connected in dependently to the top of the output capacitors and away from the higher dv/dt traces. the ovp connection then needs to be as short as possible to the pin. the agnd connection of the lower ovp components is critical for good regulation. 8. the comp network and the rest of the analog components (on iset, fpwm, fsw, etc.) should be reference to agnd. 9. the heat of the chip is main ly dissipated through the exposed thermal pad so maximizing the copper area around is a good idea. a solid ground is always helpful for the thermal and emi performance. 10. the inductor and input and output capacitors should be mounted as tight as possible, to reduce the audible noise and inductive ringing. 11. for wlcsp, the solder pad on the pcb should not be larger than the solder mask opening for the ball pad on the package. the optimal solder joint strength, it is recommended a 1:1 ratio for the two pads. generally, vias should not be used to route high- current paths. 12. the amount of copper that should be poured (thickness) depends upon the power requirement of the system. insufficient copper will increase resistance of the pcb, which will increase heat dissipation. 13. while designing the layout of sw itched controllers, do not use the auto routing function of the pcb layout software. the auto routing connects the nets with same electrical name and does not account for ideal trace lengths and positioning. general power pad design considerations figures 32 show an example of how to use vias to reduce the heat from the ic. for optimal thermal performance, use vias to distribute heat away from the ic and to a system power plane. fill the thermal pad area with vias that are spaced 3x their radius (typically), center- to-center, from each other. the via diameters should be kept small, but they should be large enough to allow solder wicking during reflow. to optimize heat transfer efficiency, do not connect vias using ?thermal relief? patterns. the vias should be directly connected to the plane with plated through-holes. connect all vias to the correct voltage potential (p ower plane) indicated in the datasheet. for the isl97692, isl97693, isl97694a, the thermal pad can be connected to ground (gnd). ch1 ch2 figure 31. figure 32. via pattern isl97692, isl97693 tqfn isl97694a tqfn
isl97692, isl97693, isl97694a 24 fn7839.5 may 1, 2014 submit document feedback pcb layout top view bottom view figure 33. example of pcb layout of isl97694a isl97694a inductor cout diode cin cout top ? layer(pgnd) bottom ? layer(agnd) pvin pgnd pgnd pvout ch1 \ 6 ovp ? resistors
isl97692, isl97693, isl97694a 25 fn7839.5 may 1, 2014 submit document feedback figure 34. example of pcb layout of isl97692 wlcsp pcb layout (continued) l1 d1 cout1 cout2 cin1 cin2 pvin pgnd_in ru rl pvout pgnd_out pgnd_out pgnd_in ? and ? pgnd_out ? connected ? via ? bottom ? layer agnd ? of ? analog ? setting ? components ? very ? close ? to ? agnd ? pin isl97692
isl97692, isl97693, isl97694a 26 fn7839.5 may 1, 2014 submit document feedback fault protection and monitoring the isl97692, isl97693, isl97694a features extensive protection functions to handle fa ilure conditions automatically. refer to figure 35 and table 8 for details of the fault protections. the led failure mode is either op en or short circuit. an open circuit failure of an led only results in the loss of one channel of leds without affecting other chan nels. similarly, a short circuit condition on a channel that result s in that channel being turned off does not affect other channels. due to the lag in boost response to any load change at its output, certain transient events (such as led current steps or significant step changes in led duty cycle) can transiently look like led fault modes. the isl97692, isl97693, isl97694a use feedback from the leds to determine when it is in a stable operating region and prevents apparent faults during these transient events from allowing any of the led stacks to fault out. see table 8 for more details. short circuit protection (scp) the short circuit detection circuit monitors the voltage on each channel and disables faulty channels, which are above the short circuit protection threshold, nomi nally 8v (the action taken is described in table 8). open circuit protection (ocp) when one of the leds becomes open circuit, it can behave as either an infinite resistance or a gradually increasing finite resistance. the isl97692, isl97693, isl97694a monitors the current in each channel such that any string, which reaches the intended output current is consid ered ?good?. should the current subsequently fall below the target, the channel will be considered an ?open circuit?. furthermore, should the boost output of the isl97692, isl97693, isl97694a reaches the v ovp limit, all channels which are not ?good? will immediately be considered as ?open circuit?. detection of an ?open circuit? channel will result in a time-out before disabling of the affected channel. overvoltage protection (ovp) the integrated ovp circuit monitors the boost output voltage, v out , and keeps the voltage at a safe level. the ovp threshold is set as equation 18: where: - 1.22v is the intended bandgap voltage by design -v ovp is the maximum boost output voltage, v out (v) -r upper is resistor from ovp pin to the boost output ( ?? -r lower is resistor from ovp pin to gnd ( ?? undervoltage lockout if the input voltage falls below the v uvlo level of ~2v, the isl97692, isl97693, isl97694a will stop switching and be reset. operation will restart only if the v in is back in the normal operating range. over-temperature protection (otp) the isl97692, isl97693, isl97694a have an over-temperature protection threshold set to +150c. if this threshold is reached, the boost stops switching and the isl97692, isl97693, isl97694a output current sinks are switched off. the isl97692, isl97693, isl97694a can be restarted by toggling v in to below the v uvlo level of ~2v, then back up to the normal input voltage level, or by power recycling v in . ovp 1.22v r upper r lower + ?? r lower ? ? = (eq. 18)
isl97692, isl97693, isl97694a 27 fn7839.5 may 1, 2014 submit document feedback figure 35. isl97692, isl97693, isl97 694a simplified fault protections qx chx dc1 pwm/oc1/sc1 ref fet driver lx imax ilimit driver fault ovp vin t2 otp thrm shdn q1 vsc ch1 vout dc2 pwm/ocx/scx temp sensor logic lx t1 otp thrm shdn o/p short fault detect logic pwm generator fault flag table 8. isl97692, isl9769 3, isl9769 4a protections table case failure mode detection mode failed channel action other channels action v out regulated by 1ch1 short circuit upper over-temperature protection limit (otp) not triggered and ch1 < 8v ch1 on and burns power. normal operation highest led string v f of other channels 2 ch1 short circuit otp triggered boost converter and channels are shut down until v in is cycled - 3 ch1 short circuit otp not triggered, ch1 > 8v ch1 disabled after 6 pwm cycle time-out normal operation highest led string v f of other channels 4 ch1 open circuit with infinite resistance otp not triggered, ch1 < 8v v out will ramp to ovp. ch1 will time-out after 6 pwm cycles and switch off. v out will then reduce to normal level normal operation highest led string v f of other channels 5output led stack voltage too high v out = v ovp any channel that is below the target current will time-out after 6 pwm cycles while v out is regulated at v ovp , and v out will then return to the normal regulation voltage required for other channels highest led string v f of channels above target current
isl97692, isl97693, isl97694a 28 fn7839.5 may 1, 2014 submit document feedback revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change may 1, 2014 fn7839.5 electrical spec table under?boost fet current limit for csp? on page 11: changed the min from 1.20 to 1.2a and typ from 1.6 to 1.6a, removed the max 2.0 value. november 27, 2013 electrical spec table on page 12 under f pwmi : added 8- bit, 10-bit and 12-bit dimming resolution. electrical spec table on page 12 under pwm acc frequency output resolution: added isl97694a with frequency range 10-bit and 12-bit. updated equation 7 on page 17: from 58.1x10 6 to r0 and added r0 for 10-bit and 12-bit of isl97694a. november 6, 2013 - updated equation 6 on page 16: from 350ns to 80ns and the effective resolution at 200hz from 13.50 bits to 15.9 bits october 28, 2013 ordering information table on page 10: change d part marking for part number ISL97692IIZ-T from tbd to 7692. electrical spec table on ?boost switching regulator? on page 11: added ?boost fe t current limit for csp?. september 19, 2013 - added isl97692 wlcsp to pin de scription, pin configuration, package diagram. - replaced ?operating conditions? to ?reco mmended operating conditions? on page 11. - added part number ISL97692IIZ-T and isl97693i rt-evz to ordering information on page 10. - added maximum average current into lx pin for wlcsp in absolute maximum ratings on page 11. - added boost fet current limit for wlcsp on page 11. - added led max current for wlcsp on page 12. - updated equation 6 on page 16. - thermal information table on page 11: added 16 bump wlscp to thermal resistance and thermal characterization sections. - pcb layout considerations updated on page 23. - example of wlcsp pcb layout added in figure 35 on page 26. - added pod w4x4.16b ?16 ball wafer level ch ip scale package (wlcsp)? to data sheet. november 30, 2012 fn7839.4 changed hbm from 2kv to 2.5kv. september 7, 2012 fn7839.3 changed cdm from 1kv to 2kv. june 28, 2012 fn7839.2 - modified title on page 1 - ivin typ lowered to 0.8ma - tenlow typ removed - added ?operation with input voltage greater than 5.5v? on page 18. - updated figure 20 - added figure 26, ?led driver operation wi th input voltage up to 26v,? on page 19. -removed ?coming soon? from isl97694a parts in ?ordering information? on page 10. may 25, 2012 fn7839.1 corrected lx pin connection in figures 1, 3, 4 and 5. moved tie point in between l1 and d1. changed title in figure 12 from ?accuracy vs wpm dimming? to ?channel matching accuracy? revised figures 9 and 10. april 16, 2012 fn7839.0 initial release.
isl97692, isl97693, isl97694a 29 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7839.5 may 1, 2014 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support
isl97692, isl97693, isl97694a 30 fn7839.5 may 1, 2014 submit document feedback package outline drawing w4x4.16b 4x4 array 16 ball wafer level chip scale package (wlcsp) rev 2, 8/13 bottom view typical recommended land pattern top view side view notes: 1. dimensions and tolerance and to lerance per asmey 14.5 - 1994. 2. dimension is measured at the maximum bump diameter parallel to primary datum z. 3. primary datum z and seating plane are defined by the spherical crowns of the bump. 4. bump position designation per jesd 95-1, spp-010. 5. all dimensions are in millimeters. 6. nsmd refers to non-solder mask defined pad design per intersil techbrief www.intersil.com/data/tb/tb451.pdf ?0.10 ?0.05 z z xy m m pin 1 package 0.10 z 0.2650.035 0.2000.030 0.5000.050 0.10 (4x) x y 4321 a b c d 3 seating plane z 1.6550.03 1.6550.03 1.200 1.200 0.400 0.400 0.200 0.290 0.240 0.400 16x 0.2650.035 0.295 2 6 nsmd 0.228 0.228 (a1 corner) outline 4
isl97692, isl97693, isl97694a 31 fn7839.5 may 1, 2014 submit document feedback package outline drawing l16.3x3d 16 lead thin quad flat no-lead plastic package rev 0, 3/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.25mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view (4x) 0.15 index area pin 1 a 3.00 b 3.00 pin #1 b 0.10 m a c 4 6 6 0.05 1 12 4 9 13 16 8 5 1.60 sq 16x 0.23 16x 0.400.10 4x 1.50 12x 0.50 (16x 0.60) ( 1.60) (2.80 typ) (16x 0.23) (12x 0.50) c 0 . 2 ref 0 . 05 max. 0 . 02 nom. 5 0.75 0.05 0.08 0.10 c c c index area see detail ?x? jedec reference draw ing: mo-220 weed. 7.
isl97692, isl97693, isl97694a 32 fn7839.5 may 1, 2014 submit document feedback package outline drawing l20.3x4a 20 lead thin quad flat no-lead plastic package rev 0, 6/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view jedec reference drawi ng: mo-220vegd-nji. 7. 3.00 4.00 a b (4x) 0.10 6 pin 1 index area c 0 . 2 ref 0 . 05 max. 0 . 00 min. 16 1 0.10 c 0.08 c seating plane pin #1 6 0.10 -0.07 a mc b 4 index area 11 6 -0.15 1.65 +0.10 20x 0.40+/-0.10 2.65 +/0.10 16x 0.50 20x 0.25 +0.05 -0.15 0.05 m c (20x 0.25) (20x 0.60) (16x 0.50) (1.65) (2.80) (2.65) (3.80) see 0.80 max c a a 17 10 7 20 detail "x" view "a-a"

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